WORKSHOP DESCRIPTION
This workshop allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost Digital Signal Processing designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.
PREREQUISITES
• Awareness on basic FPGA architecture and Xilinx FPGA design flow
• Knowledge of basic digital signal processing
Course outline:
Virtex-6 and Spartan-6 FPGA Architecture
DSP Essentials
System Generator Design Flow
Lab 1: Introduction to System Generator
FFT Basics
Lab 2: Filter and FFT Design
Concepts of Hardware co-simulation
Lab 3: DSP Targeted Design Platform
Addressing Video and image processing applications using Xilinx FPGA’s – Challenges and current trends
Lab 4: Using System Generator to Develop Virtex-6 and Spartan-6 FPGA DSP Applications
Lab 5: Video Processing and Shared Memory
Practical sessions on PlanAhead- I/O Pin Planning, Assigning I/O pins.
RESOURCE PERSONS
Ms. Sadiya, National Manager
Mr. M.S. Damodara, Product Manager
Mr.V.Senthil Murugan, Area Manager
University Program, CoreEL Tchnologies, Bangalore